OVERVIEW

The mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of components in modern SoC architectures. Based on a distributed mesh topology, it enables efficient routing of transactions across the network while maintaining low and predictable latency.

The interconnect supports AXI, AHB, APB, and AMBA CHI compliant interfaces, enabling integration of both bus-based and packet-based subsystems within a unified fabric. For CHI, dedicated ports support communication between request nodes (RN), home nodes (HN), and slave nodes (SN) using Request, Response, and Data channels.

To maximize throughput, the interconnect supports parallel processing across independent channels. AXI/AHB/APB paths support read and write channel concurrency, while the CHI path enables packet-based parallelism across its channels. Configurable transaction ordering and QoS mechanisms allow optimization of latency, fairness, and bandwidth utilization. Multiple routing algorithms are supported to improve traffic distribution and reduce congestion in the mesh

The interconnect provides flexibility for system integration through configurable register mapping and internal data width, enabling trade offs between performance, power, and area.

Robust system management features include advanced interrupt handling, per-channel watchdog timers for detecting stalled transactions, and independent software-controlled reset for each interface, enabling localized fault isolation without impacting overall system operation

Designed for complex clocking and power environments, each interface operates in an independent clock domain. Register slicing supports efficient clock-domain crossings and timing closure, while internal clock gating reduces dynamic power consumption during low-activity periods. With deterministic per-hop latency, the mesh interconnect delivers predictable performance for large-scale SoC designs.

Delivered as a synthesizable RTL IP optimized for power, performance, and area (PPA), the interconnect integrates seamlessly into AMBA based infrastructures. By combining mesh scalability, multi-protocol support including CHI, flexible routing, and rich configurability, it provides a production-ready solution for next-generation scalable SoC platforms.